| 000 | 03740cam a2200733 i 4500 | ||
|---|---|---|---|
| 001 | ocn870263361 | ||
| 003 | OCoLC | ||
| 005 | 20240523125537.0 | ||
| 006 | m o d | ||
| 007 | cr cnu|||unuuu | ||
| 008 | 140210s2014 enk ob 001 0 eng d | ||
| 040 |
_aDG1 _beng _erda _epn _cDG1 _dYDXCP _dE7B _dUMC _dOCLCF _dOCLCQ _dCOO _dOCLCQ _dDEBBG _dDG1 _dOCLCQ _dPIFBY _dOCLCQ _dSTF _dICG _dINT _dOCLCQ _dWYU _dTKN _dOCLCQ _dHS0 _dTUHNV _dOCLCO _dOCLCQ _dOCLCO _dOCLCQ _dOCLCO _dOCLCL |
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| 019 |
_a961590770 _a962707582 |
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| 020 |
_a9781118790137 _q(electronic bk.) |
||
| 020 |
_a1118790138 _q(electronic bk.) |
||
| 020 |
_a9781118790229 _q(electronic bk.) |
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| 020 |
_a1118790227 _q(electronic bk.) |
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| 020 | _a9781848215931 | ||
| 020 | _a1848215932 | ||
| 024 | 7 |
_a10.1002/9781118790229 _2doi |
|
| 029 | 1 |
_aAU@ _b000059331352 |
|
| 029 | 1 |
_aCHNEW _b000694615 |
|
| 029 | 1 |
_aCHNEW _b000694619 |
|
| 029 | 1 |
_aCHNEW _b000886753 |
|
| 029 | 1 |
_aCHNEW _b000942813 |
|
| 029 | 1 |
_aCHVBK _b480231087 |
|
| 029 | 1 |
_aDEBBG _bBV043396544 |
|
| 029 | 1 |
_aNZ1 _b15495716 |
|
| 035 |
_a(OCoLC)870263361 _z(OCoLC)961590770 _z(OCoLC)962707582 |
||
| 050 | 4 | _aQA76.54 | |
| 082 | 0 | 4 |
_a004.33 _223 |
| 049 | _aMAIN | ||
| 100 | 1 |
_aRochange, Christine, _eauthor. |
|
| 245 | 1 | 0 |
_aTime-predictable architectures / _cChristine Rochange, Sascha Uhrig, Pascal Sainrat. |
| 264 | 1 |
_aLondon, UK : _bISTE, Ltd. ; _aHoboken, NJ : _bJohn Wiley & Sons, Inc., _c2014. |
|
| 264 | 4 | _c�2014 | |
| 300 | _a1 online resource | ||
| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 490 | 1 | _aFocus series | |
| 505 | 0 | _aReal-Time Systems and Time Predictability / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Timing Analysis of Real-Time Systems / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Current Processor Architectures / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Memory Hierarchy / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Multicores / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Example Architectures / Christine Rochange, Sascha Uhrig, Pascal Sainrat. | |
| 504 | _aIncludes bibliographical references and index. | ||
| 588 | 0 | _aPrint version record. | |
| 520 | _aBuilding computers that can be used to design embedded real-time systems is the subject of this title. Real-time embedded software requires increasingly higher performances. The authors therefore consider processors that implement advanced mechanisms such as pipelining, out-of-order execution, branch prediction, cache memories, multi-threading, multicorearchitectures, etc. The authors of this book investigate the timepredictability of such schemes. | ||
| 590 |
_aJohn Wiley and Sons _bWiley Online Library: Complete oBooks |
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| 650 | 0 | _aReal-time data processing. | |
| 650 | 0 | _aComputer architecture. | |
| 650 | 6 | _aTemps r�eel (Informatique) | |
| 650 | 6 |
_aOrdinateurs _xArchitecture. |
|
| 650 | 7 |
_aComputer architecture _2fast |
|
| 650 | 7 |
_aReal-time data processing _2fast |
|
| 700 | 1 |
_aUhrig, Sascha, _eauthor. |
|
| 700 | 1 |
_aSainrat, Pascal, _eauthor. |
|
| 758 |
_ihas work: _aTime-Predictable Architectures (Text) _1https://id.oclc.org/worldcat/entity/E39PCGg7phDhTCdKJH77FjgpCP _4https://id.oclc.org/worldcat/ontology/hasWork |
||
| 776 | 0 | 8 |
_iPrint version: _aRochange, Christine. _tTime-predictable architectures _z9781848215931 _w(OCoLC)868374827 |
| 830 | 0 | _aFocus series. | |
| 856 | 4 | 0 | _uhttps://onlinelibrary.wiley.com/doi/book/10.1002/9781118790229 |
| 938 |
_aebrary _bEBRY _nebr10829797 |
||
| 938 |
_aYBP Library Services _bYANK _n10795325 |
||
| 938 |
_aYBP Library Services _bYANK _n11597401 |
||
| 938 |
_aYBP Library Services _bYANK _n12673360 |
||
| 994 |
_a92 _bINLUM |
||
| 999 |
_c12068 _d12068 |
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